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DAC650 数据表(PDF) 10 Page - Burr-Brown (TI) |
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DAC650 数据表(HTML) 10 Page - Burr-Brown (TI) |
10 / 11 page ® DAC650 10 If only one output is used, the unused output should be terminated identically. If the terminations cannot be identi- cal and the unused output must be unterminated, the termi- nation for the used output should be as close as possible to the DAC650. LAYOUT AND POWER SUPPLIES A multilayer PC board with a solid ground and power planes is recommended. An example of a typical circuit configura- tion is given in Figures 8. The DAC650 has multiple ground pins to minimize pin impedances. All of the ground pins (analog and digital both) should be connected directly to the analog ground plane at the DAC650. Wide busses for the power paths are recommended as good general practice. There are several internal power supply bypass capacitors, but external bypassing is still recom- mended. A 10 µF tantalum capacitor in parallel with a 0.01 µF chip capacitor will be sufficient in most applications. Pin 64, Analog VEE, should be connected to the same supply as the digital VEE pins (–5.2V). MAXIMIZING PERFORMANCE The DAC650 has been designed to give a very clean analog output with minimal noise, overshoot, and ringing. In addi- tion to optimizing the layout and ground of the DAC650, there are other important issues to consider when optimizing the performance of this DAC in various AC applications. The DAC650 includes an internal 50 Ω output impedance to simplify output interfacing to a 50 Ω load. Because some loads may be a complex impedance, care must be taken to match the output impedance with the load. Mismatching of impedances can cause reflections which will affect the measured AC performance parameters such as settling time, harmonic distortion, rise/fall times, etc. Often complex im- pedances can be matched by placing a variable 3 to 10pF capacitor at the output of the DAC to ground. Also, probing the output can present a complex impedance. The typical performance curves of Spurious Free Dynamic Range vs various combinations of clock rate and/or input frequency should give a general idea of the spectral perfor- mance of the DAC under system specific clock and output frequencies. We have defined Spurious Free Dynamic Range as any harmonic or non-harmonic spurs in the indicated bandwidth . In phase lock loop applications, the harmonics often fall outside the loop bandwidth of the PLL. In these cases, as well as cases where the output is filtered, Spurious BIT VOLTAGE (No External Load) CURRENT 1 1V 20mA 2 .5V 10mA 3 0.25V 5mA 4 0.125V 2.5mA 5 62.5mV 1.25mA 6 31.25mV 625 µA 7 15.625mV 312.5 µA 8 7.8125mV 156.25 µA 9 3.9063mV 78.125 µA 10 1.9531mV 39.06 µA 11 976 µV 19.53 µA 12 (LSB) 488 µV 9.76 µA TABLE I. Nominal Bit Weight Values. TABLE II. Input Code vs Output Voltage Relationships. INPUT BITS OUTPUT VOLTAGES 1 2 3 4 5 6 7 8 9 10 11 12 VOUT NVOUT 0000 0 000 0 0 0 0 +1.000 –1 + 488 µV 0000 0 000 0 0 0 1 +1 – 488 µV –1 + 976 µV 0000 0 000 0 0 1 0 +1 – 976 µV –1 + 1.464mV • • • • 0100 0 000 0 0 0 0 0.50 –0.50 + 488 µV 1000 0 000 0 0 0 0 0.000 +488 µV 1111 1 111 1 1 1 1 –1 + 488 µV +1.000 FIGURE 5. Using an RF Transformer at the Output of the DAC650. Filtering the Outputs Before the Transformer Improves the Performance in Some Applications. DAC650 V OUT 39 40 41 45 46 47 V OUT Load Mini Circuits TT5-1A FIGURE 6. A High Speed Single Ended Amplifier at the Output. The Gain is –R F/50Ω. DAC650 V OUT 39 40 41 45 46 47 V OUT OPA64X or OPA600 FIGURE 7. A High Speed Differential Amplifier at the Output. DAC650 V OUT 39 40 41 45 46 47 V OUT OPA64X or OPA600 R F |
类似零件编号 - DAC650 |
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类似说明 - DAC650 |
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