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TSC51C1XXX-A-12CGR 数据表(PDF) 11 Page - TEMIC Semiconductors |
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TSC51C1XXX-A-12CGR 数据表(HTML) 11 Page - TEMIC Semiconductors |
11 / 31 page TSC8051C1 Rev. D (14 Jan. 97) 11 MATRA MHS Table 2. Mapping of Special Function Register 0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F F8 PWM8 PWM9 PWM10 PWM11 F0 B PWM4 PWM5 PWM6 PWM7 E8 PWM0 PWM1 PWM2 PWM3 E0 ACC EICON SOCR HWDR MXCR0 D8 S1CON S1STA S1DAT PWMCON D0 PSW MXCR1 C8 C0 B8 IP B0 P3 A8 IE MSCON A0 P2 98 SCON SBUF 90 P1 88 TCON TMOD TL0 TL1 TH0 TH1 80 P0 SP DPL DPH PCON 6.8. Interrupts The TSC8051C1 has six interrupt sources, each of which can be assigned one of two priority levels. The five interrupt sources common to the 80C51 are the external interrupts (INT0 and INT1), the timer 0 and timer 1 interrupts (IT0 and IT1), and the serial I/O interrupt (RI or TI). In the TSC8051C1, the standard serial I/O is called SIO0. The SIO1 (I2C) interrupt is generated by the SI flag in the control register (S1CON SFR). This flag is set when the status register (S1STA SFR) is loaded with a valid status code. 6.8.1. Interrupt Enable Register: Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register (IE SFR). All interrupts sources can also be globally enabled or disabled by setting or clearing the EA bit in IE register. |
类似零件编号 - TSC51C1XXX-A-12CGR |
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类似说明 - TSC51C1XXX-A-12CGR |
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