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AD5570WRS-REEL7 数据表(PDF) 6 Page - Analog Devices |
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AD5570WRS-REEL7 数据表(HTML) 6 Page - Analog Devices |
6 / 24 page AD5570 Rev. 0 | Page 6 of 24 DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS VDD = +12 V ± 5%, VSS = −12 V ± 5% or VDD = +15 V ± 10%, VSS = −15 V ± 10%; VREF = 5 V; REFGND = GND = 0 V; RL = 5 kΩ, and CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted. Table 3. Parameter Limit at TMIN, TMAX Unit Description fMAX 2 MHz max SCLK frequency t1 500 ns min SCLK cycle time t2 200 ns min SCLK high time t3 200 ns min SCLK low time t4 10 ns min SYNC to SCLK falling edge setup time t5 35 ns min Data setup time t6 0 ns min Data hold time t7 45 ns min SCLK falling edge to SYNC rising edge t8 45 ns min Minimum SYNC high time t9 0 ns min SYNC rising edge to LDAC falling edge t10 50 ns min LDAC pulse width t141 200 ns max Data delay on SDO All parameters guaranteed by design and characterization. Not production tested. All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2. SDO; RPULLUP = 5 kΩ, CL = 15 pF. 1 With CL = 0 pF, t15 = 100 ns. SCLK SYNC SDIN DB15 (N) DB15 (N) DB0 (N) DB0 (N) DB15 (N+1) DB15 (N+1) DB0 (N+1) LDAC1 SDO LDAC2 NOTES 1. ASYNCHRONOUS LDAC UPDATE MODE 2. SYNCHRONOUS LDAC UPDATE MODE t1 t8 t10 t2 t3 t4 t6 t5 t9 t7 t14 Figure 3. Daisy-Chaining Timing Diagram |
类似零件编号 - AD5570WRS-REEL7 |
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类似说明 - AD5570WRS-REEL7 |
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