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SN74SSTVF16859GRG4 数据表(PDF) 1 Page - Texas Instruments |
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SN74SSTVF16859GRG4 数据表(HTML) 1 Page - Texas Instruments |
1 / 11 page SN74SSTVF16859 13BIT TO 26BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES429B − MARCH 2003 − REVISED FEBRUARY 2004 1 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D Member of the Texas Instruments Widebus Family D Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700 D Operates at 2.5 V to 2.7 V for PC3200 (QFN Package) D Pinout and Functionality Compatible With JEDEC Standard SSTV16859 D 600 ps Faster (Simultaneous Switching) Than the JEDEC Standard SSTV16859 in PC2700 DIMM Applications D 1-to-2 Outputs to Support Stacked DDR DIMMs D Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line D Outputs Meet SSTL_2 Class I Specifications D Supports SSTL_2 Data Inputs D Differential Clock (CLK and CLK) Inputs D Supports LVCMOS Switching Levels on the RESET Input D RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low D Pinout Optimizes DIMM PCB Layout D Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) − 1000-V Charged-Device Model (C101) description/ordering information This 13-bit to 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING QFN − RGQ (Tin-Pb Finish) Tape and reel SN74SSTVF16859SR SSF859 0 °C to 70°C QFN − RGQ (Matte-Tin Finish) Tape and reel SN74SSTVF16859S8 SSF859 TSSOP − DGG Tape and reel SN74SSTVF16859GR SSTVF16859 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright 2004, Texas Instruments Incorporated Widebus is a trademark of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DGG PACKAGE (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Q13A Q12A Q11A Q10A Q9A VDDQ GND Q8A Q7A Q6A Q5A Q4A Q3A Q2A GND Q1A Q13B VDDQ Q12B Q11B Q10B Q9B Q8B Q7B Q6B GND VDDQ Q5B Q4B Q3B Q2B Q1B VDDQ GND D13 D12 VCC VDDQ GND D11 D10 D9 GND D8 D7 RESET GND CLK CLK VDDQ VCC VREF D6 GND D5 D4 D3 GND VDDQ VCC D2 D1 GND VDDQ PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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类似说明 - SN74SSTVF16859GRG4 |
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