 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
AM29BDS643DT9BWLI 数据表(PDF) 11 Page - Advanced Micro Devices |
|
||||||||||||||||||||||||||||||
AM29BDS643DT9BWLI 数据表(HTML) 11 Page - Advanced Micro Devices |
|
|
11 / 46 page  Am29BDS643D 11 PRELI M INARY and drive CLK, WE# and CE# to VIL, and OE# to VIH. when writing commands or data. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word, instead of four. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. The device address space is divided into two banks: Bank A contains the boot/parameter sectors, and Bank B contains the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits re- quired to uniquely select a sector. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the VPP input. This function is primarily in- tended to allow faster manufacturing throughput at the factory. If the system asserts VID on this input, the de- vice automatically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the input to re- duce the time required for program operations. The system would use a two-cycle program command se- quence as required by the Unlock Bypass mode. Removing VID from the VPP input returns the device to normal operation. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Functions and Au- toselect Command Sequence sections for more information. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# inputs are both held at VCC ± 0.2 V. The device requires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for tACC + 60 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dr e ss ac c e s s ti mi ng s p r ov id e new d a ta w h e n addresses are changed. While in sleep mode, output data is latched and always available to the system. ICC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Input The RESET# input provides a hardware method of re- setting the device to reading array data. When RESET# is driven low for at least a period of tRP, the device immediately terminates any operation in pro gress, t r ista tes all ou tpu ts, a nd igno res a ll read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.2 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.2 V, the standby cur- rent will be greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the device requires a time of tREADY (during Embedded Algorithms) before the device is ready to read data again. If RESET# is asserted when a pro- gram or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Embedded Algorithms). The system can read data tRH after RESET# returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 12 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabl ed. T he ou tputs ar e placed i n the high impedance state. |
类似零件编号 - AM29BDS643DT9BWLI |
|
类似说明 - AM29BDS643DT9BWLI |
|
|
链接网址 |
| 隐私政策 |
| ALLDATASHEETCN.COM |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
