数据搜索系统,热门电子元器件搜索 |
|
CS61304A 数据表(PDF) 6 Page - Cirrus Logic |
|
CS61304A 数据表(HTML) 6 Page - Cirrus Logic |
6 / 32 page Any Digital Output t r t f 10% 10% 90% 90% Figure 1. Signal Rise and Fall Characteristics RCLK tpw1 tpwl1 tpwh1 HOST MODE (CLKE = 1) EXTENDED HARDWARE MODE OR HARDWARE HOST MODE (CLKE = 0) MODE OR RCLK RPOS RNEG su1 h1 tt RDATA BPV Figure 2. Recovered Clock and Data Switching Characteristics SWITCHING CHARACTERISTICS (TA = -40° to 85°C; TV+, RV+ = ±5%; Inputs: Logic 0 = 0V, Logic 1 = RV+) Parameter Symbol Min Typ Max Units SDI to SCLK Setup Time tdc 50 - - ns SCLK to SDI Hold Time tcdh 50 - - ns SCLK Low Time tcl 240 - - ns SCLK High Time tch 240 - - ns SCLK Rise and Fall Time tr, tf - - 50 ns CS to SCLK Setup Time tcc 50 - - ns SCLK to CS Hold Time tcch 50 - - ns CS Inactive Time tcwh 250 - - ns SCLK to SDO Valid (Note 33) tcdv - - 200 ns CS to SDO High Z tcdz - 100 - ns Input Valid To PCS Falling Setup Time tsu4 50 - - ns PCS Rising to Input Invalid Hold Time th4 50 - - ns PCS Active Low Time tpcsl 250 - - ns Notes: 33. Output load capacitance = 50pF. CS61304A 6 DS156PP2 CS61304A 6 DS156F1 |
类似零件编号 - CS61304A |
|
类似说明 - CS61304A |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |