CS44210-KZ datasheet(8/38 Pages) CIRRUS

部件名	CS44210-KZ

功能描述	DIGITAL PWM CONTROLLER WITH HEADPHONE MONITOR

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制造商	CIRRUS [Cirrus Logic]

网页	http://www.cirrus.com

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8 / 38 page

CS44210

8

DS539PP1

DIGITAL CHARACTERISTICS (T

A = 25° C; VL = 2.4V - 3.6V; GND=0V)

SWITCHING CHARACTERISTICS- CONTROL PORT- TWO-WIRE FORMAT

(Note 8) (TA =25° C; VL = 2.4 V - 5.0 V; Inputs: Logic 0 = GND, Logic 1 = VL, CL =30 pF)

Note:

7. VOH and VOL are tested at an output current of TBD mA.

8. The Two-Wire Format is compatible with the I2C protocol.

9. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

10. The acknowledge delay is based on MCLK and can limit the maximum transaction speed.

11.

for Single-Speed Mode and

for Double-Speed Mode.

Parameters

Symbol

Min

Typ

Max

Units

High-Level Input Voltage

VIH

0.7 x VL

-

V

Low-Level Input Voltage

VIL

--

0.3 x VL

V

Input Leakage Current

Iin

--

±10

µA

Input Capacitance

-8

-

pF

High-Level Output Voltage (Pin 15)

(Note 7)

VOH

0.7 x VL

-

V

Low-Level Output Voltage (Pin 15)

(Note 7)

VOL

--

0.3 x VL

V

High-Level Output Voltage (Pins 11, 13, 14)

(Note 7)

VOH

0.7 x VD

-

V

Low-Level Output Voltage (Pins 11, 13, 14)

(Note 7)

VOL

-

0.3 x VD

V

Parameter

Symbol

Min

Max

Unit

SCL Clock Frequency

fscl

-

100

kHz

RST Rising Edge to Start

tirs

500

-

ns

Bus Free Time Between Transmissions

tbuf

4.7

-

µs

Start Condition Hold Time (prior to first clock pulse)

thdst

4.0

-

µs

Clock Low time

tlow

4.7

-

µs

Clock High Time

thigh

4.0

-

µs

Setup Time for Repeated Start Condition

tsust

4.7

-

µs

SDA Hold Time from SCL Falling

(Note 9)

thdd

0-

µs

SDA Setup time to SCL Rising

tsud

250

-

ns

Rise Time of SCL and SDA

trc, trc

-1

µs

Fall Time SCL and SDA

tfc, tfc

-

300

ns

Setup Time for Stop Condition

tsusp

4.7

-

µs

Acknowledge Delay from SCL Falling

(Note 10)

tack

-

(Note 11)

ns

5

256

Fs

×

---------------------

5

128

F s

×

---------------------

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