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CS5511-ASZ 数据表(PDF) 7 Page - Cirrus Logic |
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CS5511-ASZ 数据表(HTML) 7 Page - Cirrus Logic |
7 / 24 page CS5510/11/12/13 DS337F3 7 SWITCHING CHARACTERISTICS - CS5510/12 (TA = 25° C; V+ = 5 V ±5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; CL = 50 pF) Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or 200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded linearity specifications, as shown in Figures 14 and 15. 21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 22. On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for tSLP or longer, the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for tWAKE or longer. Parameter Symbol Min Typ Max Unit Master Clock Timing Master Clock Frequency (CS5510) (Note 20) SCLK 10 32.768 130 kHz Master Clock Frequency (CS5512) (Note 20) SCLK 10 32.768 200 kHz Master Clock Duty Cycle 40 - 60 % Rise Times (Note 21) CSB SCLK SDO trise - - - - - 50 1.0 10 - µs µs ns Fall Times (Note 21) CSB SCLK SDO tfall - - - - - 50 1.0 10 - µs µs ns Serial Port Timing Serial Clock Frequency (CS5510) (Note 22) SCLK 10 32.768 130 kHz Serial Clock Frequency (CS5512) (Note 22) SCLK 10 32.768 200 kHz SCLK High to Enter Sleep (Note 22) tSLP 200 - 2000 µs SCLK Low to Exit Sleep (Note 22) tWAKE 10 - - µs Serial Clock Pulse Width High Pulse Width Low t1 t2 2 2 - - 60 60 µs µs SDO Read Timing CS to Data Valid t3 -- 150 ns SCLK Falling to New Data Bit t4 -- 150 ns CS Rising to SDO Hi-Z t5 -- 150 ns CS Falling to SCLK Rising t11 200 - - ns |
类似零件编号 - CS5511-ASZ |
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类似说明 - CS5511-ASZ |
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