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CAT1321UI-45TSSOP 数据表(PDF) 9 Page - Catalyst Semiconductor |
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CAT1321UI-45TSSOP 数据表(HTML) 9 Page - Catalyst Semiconductor |
9 / 18 page 9 Advance Information CAT1320, CAT1321 Doc No. 25085, Rev. 00 ACKNOWLEDGE After a successful data transfer, each receiving device is required to generate an acknowledge. The acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data. The CAT1320/21 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. When the CAT1320/21 begins a READ mode it transmits 8 bits of data, releases the SDA line and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT1320/21 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. WRITE OPERATIONS Byte Write In the Byte Write mode, the Master device sends the START condition and the slave address information (with the R/ W bit set to zero) to the Slave device. After the Slave generates an acknowledge, the Master sends two 8-bit address bytes that are to be written into the address pointers of the device. After receiving another acknowledge from the Slave, the Master device transmits the data to be written into the addressed memory location. The CAT1320/ 21 acknowledges once more and the Master generates the STOP condition. At this time, the device begins an internal programming cycle to non-volatile memory. While the cycle is in progress, the device will not respond to any request from the Master device. Figure 7. Slave Address Bits CAT Default Configuration 1010 A2 A1 A0 R/W START BIT SDA STOP BIT SCL Figure 5. Start/Stop Timing ACKNOWLEDGE 1 START SCL FROM MASTER 89 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER Figure 6. Acknowledge Timing |
类似零件编号 - CAT1321UI-45TSSOP |
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类似说明 - CAT1321UI-45TSSOP |
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