数据搜索系统,热门电子元器件搜索 |
|
ADV7305AKST 数据表(PDF) 7 Page - Analog Devices |
|
ADV7305AKST 数据表(HTML) 7 Page - Analog Devices |
7 / 68 page REV. A ADV7304A/ADV7305A –7– t9 t11 t10 t12 t13 t14 CLKIN_A C9–C0 P_HSYNC, P_VSYNC, P_BLANK CONTROL I/PS Y9–Y0 CONTROL O/PS S_HSYNC, S_VSYNC t 9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME S9–S0 G0 G1 G2 Gxxx Gxxx B0 B1 B2 B3 Bxxx Bxxx R0 R1 R2 G3 Rxxx Rxxx Figure 4. HD 4:4:4 RGB Input Data Format Timing Diagram, HD RGB Input Enabled (Input Mode at Subaddress 01h = 001 or 010) t9 t11 t10 t12 t11 t12 t13 t14 CLKIN_B Y9–Y0 P_HSYNC, P_VSYNC, P_BLANK CONTROL I/PS CONTROL O/PS S_HSYNC, S_VSYNC t 9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME Cb0 Y0 Cr0 Y1 Crxxx Yxxx Figure 5. PS 4:2:2 1 10-Bit Interleaved @ 27 MHz, Input Mode: PS Input Only (Input Mode at Subaddress 01h = 100) |
类似零件编号 - ADV7305AKST |
|
类似说明 - ADV7305AKST |
|
|
链接网址 |
隐私政策 |
ALLDATASHEETCN.COM |
ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |