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ADV7305A 数据表(PDF) 8 Page - Analog Devices |
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ADV7305A 数据表(HTML) 8 Page - Analog Devices |
8 / 68 page REV. A ADV7304A/ADV7305A –8– t9 t11 t10 t12 Cb0 Y0 Cr0 Y1 Crxxx Yxxx t14 t13 CLKIN_A Y9–Y0 P_HSYNC, P_VSYNC, P_BLANK CONTROL I/PS CONTROL O/PS S_HSYNC, S_VSYNC t 9 = CLOCK HIGH TIME, t10 = CLOCK LOW TIME, t11 = DATA SETUP TIME, t12 = DATA HOLD TIME Figure 6. PS 4:2:2 1 10-Bit Interleaved @ 54 MHz, Input Mode: PS 54 MHz Input (Input Mode at Subaddress 01h = 111) t9 t11 t10 t12 Cb Y Cr Y Cb Y t13 t14 CLKIN_A S9–S2 S_HSYNC, S_VSYNC, S_BLANK CONTROL I/PS CONTROL O/PS S_HSYNC, S_VSYNC IN SLAVE MODE IN MASTER/SLAVE MODE WITH EAV/SAV Figure 7. 8-Bit SD Pixel Input Timing Diagram, Input Mode: SD Input Only (Input Mode at Subaddress 01h = 000) |
类似零件编号 - ADV7305A |
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类似说明 - ADV7305A |
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