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LM2502SM 数据表(PDF) 8 Page - National Semiconductor (TI) |
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LM2502SM 数据表(HTML) 8 Page - National Semiconductor (TI) |
8 / 27 page Switching Characteristics (Continued) Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter Conditions Min Typ Max Units POWER UP TIMING(Note 5) MPL POWER OFF TIMING t PAZ Disable Time to Power Down Figure 7, This parameter is functionally tested by the I DDZ parameter. (Note 6) 50 ms Recommended Input Timing Requirements Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter Conditions Min Typ Max Units MASTER REFERENCE CLOCK (CLK) f CLK Clock Frequency See Table 10 (Note 5) 3 25 MHz t CP Clock Period 40 333 ns CLK DC Clock Duty Cycle 40 50 60 % t T Clock Transition Times (Rise or Fall, 20%–80%) 114 ns Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. Note 2: Typical values are given for VDDIO = 1.8V and VDD = VDDA = 3.0V and TA = 25˚C. Note 3: Current into a device pin is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to Ground unless otherwise specified. Note 4: UFBGA assumes 4 layer PCB, LLP assumes 2 layer PCB for thermal calculations. Note 5: This parameter is Guaranteed by Design (GBD) based on simulation or bench characterization. Note 6: This parameter is guaranteed by a ATE tester delay, actual turn off time is faster. Note 7: Typical supply condition is VDDIO = 1.8V and VDD =VDDA = 3.0V, Maximum supply condition is VDDIO =VDD =VDDA = 3.3V for the IDD parameter. Timing Diagrams 20093316 FIGURE 1. Serial Data Valid — Master to Slave 20093318 FIGURE 2. Slave Output Rise and Fall Time www.national.com 8 |
类似零件编号 - LM2502SM |
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类似说明 - LM2502SM |
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