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CS61318-IP 数据表(PDF) 1 Page - Cirrus Logic |
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CS61318-IP 数据表(HTML) 1 Page - Cirrus Logic |
1 / 28 page Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. 1 Copyright © Cirrus Logic, Inc. 1999 (All Rights Reserved) P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com CS61318 E1 Line Interface Unit Features s E1 Line Interface Unit s No Crystal Needed for Jitter Attenuation s Meets CTR-12/TBR-12 Jitter Tolerance and Attenu- ation Requirements s Meets ITU-T G.775 Requirements for LOS and AIS s Meets the BS6450 Transmitter Short-Circuit Requirements for E1 Applications s AWG for User Programmable Pulse Shapes s Line Quality Monitoring Function s TX Driver High Impedance / Low Power Control s AIS and LOS Monitoring s Generation and Detection of Loop Up / Loop Down Signaling s Selectable HDB3 Encoding/Decoding s Selectable Unipolar or Bipolar I/O s Compliant with: — ITU-T Recommendations: G.703, G.732, G.775, I.431 — ETSI ETS 300 011, 300 233, CTR 12, TBR 13 — TR-NET-00499 Description The CS61318 is an E1 primary rate line interface unit. This device combines the complete analog transmit and receive circuitry for a single, full-duplex interface E1 rates. The device provides jitter attenuation compliant to CTR12/TBR13 without requiring an external crystal. Al- so, the CS61318 is pin and function compatible with the Level One LXT318. In addition to a basic hardware control mode, a host mode is available that gives the user an enhanced func- tionality via a serial microprocessor interface. The extended features include custom pulse shape genera- tion, AIS and LOS monitoring functions, signal strength monitoring, and generation and detection of loop up and loop down codes. ORDERING INFORMATION CS61318-IL 28-pin PLCC CS61318-IP 28-pin PDIP TCLK TDATA/TPOS UBS/TNEG JASEL RCLK RDATA/RPOS BPV/RNEG INT/NLOOP LOS 2 3 4 E N C O D E R 11 REMOTE LOOPBACK 8 7 6 D E C O D E R 23 12 INBAND NLOOP & LOS PROCESSOR RECEIVE CLOCK GENERATOR 9 10 XTALIN XTALOUT 5 21 221415 MODE RV+ RGND TGND TV+ JITTER ATTEN TIMING & DATA RECOVERY LOS/ NLOOP Clear REGISTERS & CONTROL LOGIC TAOS Enable JITTER ATTEN TRANSMIT TIMING & CONTROL PULSE SHAPING CIRCUITRY ROM / RAM LINE DRIVERS SERIAL PORT LLOOP Enable LOCAL LOOPBACK (ANALOG) EQUALIZER CONTROL SLICERS & PEAK DETECT NOISE & CROSSTALK FILTERS MAGNITUDE EQUALIZER AGC 13 16 28 26 27 24 25 18 19 20 1 TTIP TRING CLKE/TAOS CS/RLOOP SCLK/LLOOP SDI/LBO1 SDO/LBO2 LATN RTIP RRING MCLK LOCAL LOOPBACK (DIGITAL) DS441PP2 AUG ‘99 |
类似零件编号 - CS61318-IP |
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类似说明 - CS61318-IP |
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