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GD25B257D 数据表(PDF) 26 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD25B257D 数据表(HTML) 26 Page - GigaDevice Semiconductor (Beijing) Inc. |
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26 / 92 page  3.3V Uniform Sector Dual and Quad Serial Flash GD25B257D 26 8.6. Read Extended Register (C8H) Extended Register contains ECC Status Bits, several device configuration bits, and Address Bit A24. The Read Extended Register instruction is entered by driving CS# low and shifting the instruction code “C8H” into the SI pin on the rising edge of SCLK. The Extended Register bits are then shifted out on the SO pin at the falling edge of SCLK with most significant bit (MSB) first as shown below. When the device is in the 4-Byte Address Mode, the value of A24 Bit is not ignored. Figure 8 Read Extended Register Sequence Diagram 8.7. Write Extended Register (C5H or 56H) The Write Extended Register command could be executed no matter the Write Enable Latch (WEL) bit is 0 or 1. The Write Extended Register instruction is entered by driving CS# low, sending the instruction code “C5/56H”, and then writing the Extended Register data Byte as illustrated below. C5H is used to write A24 bit in the Extended Register. 56H is used to write EA5-EA2 (DLP, ECS bits). Upon power up or the execution of a Software/Hardware Reset, the Extended Register bit values will be cleared to 0. Figure 9 Write Extended Register Sequence Diagram Command 0 1 2 3 4 5 6 7 C8H CS# SCLK SI SO High-Z 8 9 10 11 12 13 14 15 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 MSB Extended Addr. Register Out MSB Extended Addr. Register Out Command 0 1 2 3 4 5 6 7 C5/56H CS# SCLK SI SO High-Z 8 9 10 11 12 13 14 15 MSB 7 6 5 4 3 2 1 0 Extended Addr. Register In |
类似说明 - GD25B257D |
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