TLF9829

April 1992

DM54LS323DM74LS323

8-Bit Universal ShiftStorage Register

with Synchronous Reset and Common IO Pins

General Description

The ’LS323 is an 8-bit universal shiftstorage register with

TRI-STATE

outputs Its function is similar to the ’LS299

with the exception of Synchronous Reset Parallel load in-

puts and flip-flop outputs are multiplexed to minimize pin

count Separate inputs and outputs are provided for flip-

flops Q0 and Q7 to allow easy cascading Four operation

modes are possible hold (store) shift left shift right and

parallel load All modes are activated on the LOW-to-HIGH

transition of the Clock

Features

Y

Common IO for reduced pin count

Y

Four operation modes shift left shift right parallel load

and store

Y

Separate continuous inputs and outputs from Q0 and

Q7 allow easy cascading

Y

Fully synchronous reset

Y

TRI-STATE outputs for bus oriented applications

Connection Diagram

Dual-In-Line Package

TLF9829 – 1

Order Number DM54LS323J DM54LS323W DM74LS323WM or DM74LS323N

See NS Package Number J20A M20B N20A or W20A

Pin Names

Description

CP

Clock Pulse Input (Active Rising Edge)

Serial Data Input for Right Shift

Serial Data Input for Left Shift

S0 S1

Mode Select Inputs

SR

Synchronous Reset Input (Active LOW)

OE1 OE2

TRI-STATE Output Enable Inputs (Active LOW)

IO0 – IO7

Parallel Data Inputs or TRI-STATE

Parallel Outputs

Q0 Q7

Serial Outputs

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M115Printed in U S A