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MC7455ARX1000LG 数据表(PDF) 3 Page - Freescale Semiconductor, Inc |
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MC7455ARX1000LG 数据表(HTML) 3 Page - Freescale Semiconductor, Inc |
3 / 64 page MPC7455 RISC Microprocessor Hardware Specifications, Rev. 4.1 Freescale Semiconductor 3 Features The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus protocol and a subset of the 60x bus protocol to main memory and other system resources. The L3 interface supports 1 or 2 Mbytes of external SRAM for L3 cache data. Note that the MPC7455 is footprint-compatible with the MPC7450 and MPC7451, and the MPC7445 is footprint-compatible with the MPC7441. 2Features This section summarizes features of the MPC7455 implementation of the PowerPC architecture. Major features of the MPC7455 are as follows: • High-performance, superscalar microprocessor — As many as four instructions can be fetched from the instruction cache at a time — As many as three instructions can be dispatched to the issue queues at a time — As many as 12 instructions can be in the instruction queue (IQ) — As many as 16 instructions can be at some stage of execution simultaneously — Single-cycle execution for most instructions — One instruction per clock cycle throughput for most instructions — Seven-stage pipeline control • Eleven independent execution units and three register files — Branch processing unit (BPU) features static and dynamic branch prediction – 128-entry (32-set, four-way set-associative) branch target instruction cache (BTIC), a cache of branch instructions that have been encountered in branch/loop code sequences. If a target instruction is in the BTIC, it is fetched into the instruction queue a cycle sooner than it can be made available from the instruction cache. Typically, a fetch that hits the BTIC provides the first four instructions in the target stream. – 2048-entry branch history table (BHT) with two bits per entry for four levels of prediction—not-taken, strongly not-taken, taken, and strongly taken – Up to three outstanding speculative branches – Branch instructions that do not update the count register (CTR) or link register (LR) are often removed from the instruction stream. – Eight-entry link register stack to predict the target address of Branch Conditional to Link Register (bclr) instructions — Four integer units (IUs) that share 32 GPRs for integer operands – Three identical IUs (IU1a, IU1b, and IU1c) can execute all integer instructions except multiply, divide, and move to/from special-purpose register instructions – IU2 executes miscellaneous instructions including the CR logical operations, integer multiplication and division instructions, and move to/from special-purpose register instructions — Five-stage FPU and a 32-entry FPR file – Fully IEEE 754-1985-compliant FPU for both single- and double-precision operations – Supports non-IEEE mode for time-critical operations – Hardware support for denormalized numbers |
类似零件编号 - MC7455ARX1000LG |
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类似说明 - MC7455ARX1000LG |
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