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93AA66ATEMS 数据表(PDF) 10 Page - Microchip Technology

部件名 93AA66ATEMS
功能描述  4K Microwire Compatible Serial EEPROM
Download  24 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

93AA66ATEMS 数据表(HTML) 10 Page - Microchip Technology

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93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C
DS21795B-page 10
 2003 Microchip Technology Inc.
2.9
WRITE ALL (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
For 93AA66A/B/C and 93LC66A/B/C devices, after the
last data bit is clocked into DI, the falling edge of CS
initiates the self-timed auto-erase and programming
cycle. For 93C66A/B/C devices, the self-timed auto-
erase and programming cycle is initiated by the rising
edge of CLK on the last data bit. Clocking of the CLK
pin is not necessary after the device has entered the
WRAL cycle. The WRAL command does include an
automatic ERAL cycle for the device. Therefore, the
WRAL
instruction does not require an ERAL instruction
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
Note:
Issuing a Start bit and then taking CS low
will clear the READY/BUSY status from
DO.
VCC must be
≥ 4.5V for proper operation of WRAL.
FIGURE 2-10:
WRAL TIMING FOR 93AA AND 93LC DEVICES
FIGURE 2-11:
WRAL TIMING FOR 93C DEVICES
CS
CLK
DI
DO
HIGH-Z
1
0
0
01
X
•••
X
Dx
•••
D0
HIGH-Z
BUSY
READY
TWL
VCC must be
≥ 4.5V for proper operation of WRAL.
TCSL
TSV
TCZ
CS
CLK
DI
DO
HIGH-Z
1
0
0
01
X
•••
X
Dx
•••
D0
HIGH-Z
BUSY
READY
TWL
TCSL
TSV
TCZ


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