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CAT25C11U14E-1.8TE13 数据表(PDF) 9 Page - Catalyst Semiconductor |
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CAT25C11U14E-1.8TE13 数据表(HTML) 9 Page - Catalyst Semiconductor |
9 / 12 page 9 CAT25C11/03/05/09/17 Doc. No. 1017, Rev. J Figure 7. WRSR Instruction Timing DESIGN CONSIDERATIONS The CAT25C11/03/05/09/17 powers up in a write dis- able state and in a low power standby mode. A WREN instruction must be issued to perform any writes to the device after power up. Also,on power up CS should be brought low to enter a ready state and receive an instruction. After a successful byte/page write or status register write the CAT25C11/03/05/09/17 goes into a write disable mode. CS must be set high after the proper number of clock cycles to start an internal write cycle. Access to the array during an internal write cycle is ignored and programming is continued. On power up, SO is in a high impedance. If an invalid op code is Figure 8. Page Write Instruction Timing 0 1 2 345 67 8 10 911 12 13 14 SCK SI MSB HIGH IMPEDANCE DATA IN 15 SO CS 7 6 5 4 3 2 10 00 0 00 0 0 1 OPCODE Note: Dashed Line= mode (1, 1) – ––– Note: Dashed Line= mode (1, 1) – – – – received, no data will be shifted into the CAT25C11/03/ 05/09/17, and the serial output pin (SO) will remain in a high impedance state until the falling edge of CS is detected again. When powering down, the supply should be taken down to 0V, so that the CAT25C11/03/05/09/17 will be reset when power is ramped back up. If this is not possible, then, following a brown-out episode, the CAT25C11/ 03/05/09/17 can be reset by refreshing the contents of the Status Register (See Application Note AN10). SK SI SO 00 00 X* 0 1 0 Data Byte 1 012345678 21 22 23 24-31 32-39 Data Byte 2 Data Byte 3 Data Byte N CS OPCODE 7..1 0 24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1 DATA IN HIGH IMPEDANCE BYTE ADDRESS* *Please check the Byte Address Table. AN A0 *X = 0 for CAT25C11, CAT25C03, CAT25C09 and CAT25C17; X = A8 for CAT25C05 |
类似零件编号 - CAT25C11U14E-1.8TE13 |
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类似说明 - CAT25C11U14E-1.8TE13 |
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