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August 2004

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HIGH SPEED:

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5V TOLERANT INPUTS

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POWER-DOWN PROTECTION ON INPUTS

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INPUT VOLTAGE LEVEL:

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LOW POWER DISSIPATION:

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LOW NOISE:

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SYMMETRICAL OUTPUT IMPEDANCE:

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BALANCED PROPAGATION DELAYS:

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OPERATING VOLTAGE RANGE:

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 273

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IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVX273 is a low voltage CMOS OCTAL

D-TYPE FLIP-FLOP WITH CLEAR fabricated with

sub-micron silicon gate and double-layer metal

power, battery operated and low noise 3.3V

applications.

Information signals applied to D inputs are

transferred to the Q outputs on the positive going

edge of the clock pulse.

When the CLEAR input is held low, the Q outputs

are held low independently of the other inputs.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage.

This device can be used to interface 5V to 3V. It

combines high speed performance with the true

CMOS low power consumption.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74LVX273

LOW VOLTAGE CMOS OCTAL D-TYPE FLIP-FLOP

WITH CLEAR (5V TOLERANT INPUTS)

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74LVX273MTR

TSSOP

74LVX273TTR

TSSOP

SOP

Rev. 3