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MC1151A-E 数据表(PDF) 6 Page - List of Unclassifed Manufacturers |
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MC1151A-E 数据表(HTML) 6 Page - List of Unclassifed Manufacturers |
6 / 70 page 6 Timing Interval T# Min. Max. Units Command Byte Write Timing ~HostSlct Hold Time T6 15 2000 (note 3) nS ~HostSlct Setup Time T7 10 nS HostCmd Setup Time T8 10 nS Host Cmd Hold Time T9 25 nS HostRdy Delay Time T13 70 nS ~HostWrite Pulse Width T14 50 nS Write Data Setup Time T15 35 nS Write Data Hold Time T16 30 nS Data Word Read Timing ~HostSlct Hold Time T6 15 2000 (note 3) nS ~HostSlct Setup Time T7 (read only) - 20 nS HostCmd Setup Time T8 (read only) - 20 nS HostCmd Hold Time T9 25 nS Read Data Access Time T10 50 nS Read Data Hold Time T11 10 nS ~HostRead high to HI-Z Time T12 50 nS HostRdy Delay Time T13 70 nS Read Recovery Time T17 60 nS Data Word Write Timing ~HostSlct Hold Time T6 15 2000 (note 3) nS ~HostSlct Setup Time T7 10 nS HostCmd Setup Time T8 10 nS HostCmd Hold Time T9 25 nS HostRdy Delay Time T13 70 nS ~HostWrite Pulse Width T14 50 nS Write Data Setup Time T15 35 nS Write Data Hold Time T16 30 nS Write Recovery Time T18 60 nS DAC Interface Timing I/OAddr Stable to ~I/OWrite setup time T19 35 nS ~I/OWrite Pulse Width T20 56 95 nS Data Hold Time After ~I/OWrite T21 17 nS ClkOut Low to I/OAddr stable T22 10 40 nS ClkOut Low to ~I/OWrite Low T23 75 92 nS ClkOut Low to Data Valid T24 92 nS ClkOut Cycle Time T25 160 typical (note 4) nS I/OAddr Stable to DACSlct High T26 66 nS ~I/OWrite Low to DACSlct High T27 44.5 nS PWM Output Timing PWM Output Frequency 24.5 Khz note 1 ~HostSlct and HostCmd may optionally be de-asserted if setup and hold times are met. note 2 Chip-set performance figures and timing information valid at Fclk = 25.0 only. For timing information & performance parameters at Fclk < 25.0 Mhz, call PMD. note 3 Two micro seconds maximum to release interface before chip set responds to command note 4 ClkOut from CP is 1/4 frequency of ClkIn (CP chip). |
类似零件编号 - MC1151A-E |
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类似说明 - MC1151A-E |
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