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AD5392BST-5 数据表(PDF) 9 Page - Analog Devices |
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AD5392BST-5 数据表(HTML) 9 Page - Analog Devices |
9 / 40 page AD5382 Rev. 0 | Page 9 of 40 1LDAC ACTIVE DURING BUSY 2LDAC ACTIVE AFTER BUSY BUSY SYNC LDAC1 LDAC2 CLR VOUT VOUT2 VOUT1 DIN SCLK t7 t8 t9 t4 t3 t1 t2 t5 t17 t17 t12 t13 t18 t19 t16 t14 t10 t15 t13 t11 t6 DB0 DB23 24 24 Figure 3. Serial Interface Timing Diagram (Standalone Mode) t7A 24 48 SCLK SYNC DIN SDO DB23 DB0 DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ UNDEFINED NOP CONDITION SELECTED REGISTER DATA CLOCKED OUT Figure 4. Serial Interface Timing Diagram (Data Readback Mode) t22 t13 t23 t21 t2 t3 t20 t8 t9 t7 t4 t1 SCLK SYNC SDO DIN LDAC 48 24 DB23 DB0 DB0 DB23 DB23 DB0 INPUT WORD FOR DAC N INPUT WORD FOR DAC N+1 UNDEFINED INPUT WORD FOR DAC N Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode) |
类似零件编号 - AD5392BST-5 |
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类似说明 - AD5392BST-5 |
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