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TPS659112A2ZRC 数据表(PDF) 93 Page - Texas Instruments |
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TPS659112A2ZRC 数据表(HTML) 93 Page - Texas Instruments |
93 / 143 page 93 TPS65911 www.ti.com SWCS049S – JUNE 2010 – REVISED AUGUST 2018 Submit Documentation Feedback Product Folder Links: TPS65911 Detailed Description Copyright © 2010–2018, Texas Instruments Incorporated Table 6-55. DCDCCTRL_REG Address Offset 0x3E Instance RESET DOMAIN: bits [7:3]: TURNOFF OFF RESET bits [2:0]: GENERAL RESET Description DCDC control register Type RW 7 6 5 4 3 2 1 0 Reserved TRACK VDD2_PSKIP VDD1_PSKIP VIO_PSKIP DCDCCKEXT DCDCCKSYNC Bits Field Name Description Type Reset 7 Reserved Reserved bit RO R returns 0s 0 6 TRACK 0 = Normal LDO operation without tracking 1 = Tracking mode: LDO4 output follows VDD1 setting when VDD1 active. See Section 6.5.3.14 for more information. RW 0 5 VDD2_PSKIP VDD2 pulse skip mode enable (EEPROM bit) Default value: See boot configuration RW 1 4 VDD1_PSKIP VDD1 pulse skip mode enable (EEPROM bit) Default value: See boot configuration RW 1 3 VIO_PSKIP VIO pulse skip mode enable (EEPROM bit) Default value: See boot configuration RW 1 2 DCDCCKEXT This signal control the muxing of the GPIO2 pad: When 0: this pad is a GPIO When 1: this pad is used as input for an external clock used for the synchronisation of the DCDCs RW 0 1:0 DCDCCKSYNC DCDC clock configuration: DCDCCKSYNC[1:0] = 00: no synchronization of DCDC clocks DCDCCKSYNC[1:0] = 01: DCDC synchronous clock with phase shift DCDCCKSYNC[1:0] = 10: no synchronization of DCDC clocks DCDCCKSYNC[1:0] = 11: DCDC synchronous clock RW 0x1 |
类似零件编号 - TPS659112A2ZRC |
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类似说明 - TPS659112A2ZRC |
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