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M41T62 数据表(PDF) 9 Page - STMicroelectronics |
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M41T62 数据表(HTML) 9 Page - STMicroelectronics |
9 / 33 page 9/33 M41T62/63/64/65 Acknowledge. Each byte of eight bits is followed by one Acknowledge Bit. This Acknowledge Bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge relat- ed clock pulse. A slave receiver which is ad- dressed is obliged to generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is a stable Low dur- ing the High period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master receiver must sig- nal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this case the transmitter must leave the data line High to enable the master to generate the STOP condition. Figure 16. Serial Bus Data Transfer Sequence Figure 17. Acknowledgement Sequence AI00587 DATA CLOCK DATA LINE STABLE DATA VALID START CONDITION CHANGE OF DATA ALLOWED STOP CONDITION AI00601 DATA OUTPUT BY RECEIVER DATA OUTPUT BY TRANSMITTER SCL FROM MASTER START CLOCK PULSE FOR ACKNOWLEDGEMENT 12 89 MSB LSB |
类似零件编号 - M41T62 |
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类似说明 - M41T62 |
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