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AD5263BRU50-REEL7 数据表(PDF) 3 Page - Analog Devices |
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AD5263BRU50-REEL7 数据表(HTML) 3 Page - Analog Devices |
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3 / 6 page  PRELIMINARY TECHNICAL DATA Quad +15V Digital Potentiometers AD5263 08 AUG ’02, REV PrD - 3 - ELECTRICAL CHARACTERISTICS 20K, 50K, 200K OHM VERSION (V DD = +5V, VSS = -5V, VL = +5V, VA = +VDD, VB = 0V, -40°C < TA < +125°C unless otherwise noted.) Parameter Symbol Conditions Min Typ 1 Max Units SPI (DIS=’0’) INTERFACE TIMING CHARACTERISTICS applies to all parts (Notes 6,12) Input Clock Pulse Width tCH,tCL Clock level high or low 50 ns Data Setup Time tDS 20 ns Data Hold Time tDH 20 ns CLK to SDO Propagation Delay13 tPD RL = 1KΩ, CL < 20pF 1 150 ns CS Setup Time tCSS 20 ns CS High Pulse Width tCSW 40 ns Reset Pulse Width tRS 90 ns CLK Fall to CS Rise Hold Time tCSH 0 ns CS Rise to Clock Rise Setup tCS1 10 ns I2C (DIS=’1’) INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12) SCL Clock Frequency fSCL 0 400 KHz tBUF Bus free time between STOP & START t1 1.3 µs tHD;STA Hold Time (repeated START) t2 After this period the first clock pulse is generated 0.6 µs tLOW Low Period of SCL Clock t3 1.3 µs tHIGH High Period of SCL Clock t4 0.6 µs tSU;STA Setup Time For START Condition t5 0.6 µs tHD;DAT Data Hold Time t6 0 0.9 µs tSU;DAT Data Setup Time t7 100 ns tF Fall Time of both SDA & SCL signals t8 300 ns tR Rise Time of both SDA & SCL signals t9 300 ns tSU;STO Setup time for STOP Condition t10 0.6 µs NOTES: 1. Typicals represent average readings at +25°C and VDD = +5V, VSS = -5V. 2. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD=+5V, VSS=-5V. 3. VAB = VDD, Wiper (VW) = No connect 4. INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of ±1LSB maximum are Guaranteed Monotonic operating conditions. 5. Resistor terminals A, B, W have no limitations on polarity with respect to each other. 6. Guaranteed by design and not subject to production test. 7. Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode. 8. Worst case supply current consumed when input all logic-input levels set at 2.4V, standard characteristic of CMOS logic. 9. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation. 10. All dynamic characteristics use VDD = +5V, VSS = -5V, VL = +5V. 11. Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change. 12. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics are measured using VL = +5V. 13. Propagation delay depends on value of VDD, RL, and CL see applications text. 14. The AD5260/AD5262 contains 1,968 transistors. Die Size: 89mil x 105mil, 9,345sq. mil. |
类似零件编号 - AD5263BRU50-REEL7 |
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类似说明 - AD5263BRU50-REEL7 |
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