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FM573 数据表(PDF) 7 Page - List of Unclassifed Manufacturers

部件名 FM573
功能描述  Nonvolatile Octal Latch/Register
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FM573 数据表(HTML) 7 Page - List of Unclassifed Manufacturers

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Ramtron
FM573/574
27 March 2001
7/10
AC Parameters TA = -40
° C to + 85° C, CL = 50 pF unless otherwise specified
VDD=2.7V – 3.6V
VDD=5.0V +/- 10%
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
fMAX
Maximum clock frequency
12
30
MHz
tCW
Clock minimum pulse width
30
8
ns
tPD
Propagation delay Dn to Qn
Propagation delay C to Qn
80
33
ns
tEN
Output enable time /OE to Qn
70
28
ns
tDIS
Output disable /OE to Qn Hi-Z
60
25
ns
1
tDS
Data setup Dn to C low (573)
Data setup Dn to C
↑ (574)
5
5
ns
tDH
Data hold Dn after C low (573)
Data hold after C high (574)
7
5
ns
Notes:
1
This parameter is characterized but not tested.
Power Cycling and Data Retention TA = -40
° C to + 85° C, VDD = 2.7V to 5.5V unless otherwise specified
VDD=2.7V – 3.6V
VDD=5.0V +/- 10%
Symbol
Parameter
Min
Max
Min
Max
Units
Notes
Nonvolatile data retention
1
1
Year
1
Latched state changes
1E10
1E10
Changes
2
tPDS
Last state change to VMIN
2
1
µS
3
tRES
VMIN to output valid
1
1
µS
4
tPUH
VMIN to first user write
1.5
1.5
µS
4,5
Notes:
1.
Data retention is measured from the last state change, and is the time that a state will be retained at 85
° C and
correctly restored on power-up. The process of powering up (and reading the nonvolatile state) refreshes the
stored state and re -starts the data retention period even if the state is unchanged.
2.
The nonvolatile elements are written when the latched state changes. Changes on either Dn or Qn that are not
latched have no effect.
3.
The last write to the nonvolatile latch element must occur prior to reaching VMIN during a power down.
4.
After the power supply reaches approximately VMIN during a power up, the nonvolatile latch is read and the
value restored to the user latch. This spec. provides the time needed to restore the FM573/FM574 pins to the
restored state depending on the state of /OE.
5.
The user should not attempt to write during the restore process. In particular, powering up in transparent mode
(FM573) defeats the purpose of using a nonvolatile latch.
Capacitance TA = 25
° C , f=1.0 MHz, VDD = 5V
Symbol
Parameter
Max
Units
Notes
CIN
Input capacitance
6
pF
1
Notes
1
This parameter is characterized but not tested.
Equivalent AC Load Circuit
AC Test Conditions
Input Pulse Levels
0.1VDD to 0.9VDD
Input rise and fall times
10 ns
Input and output timing levels
0.3VDD, 0.7 VDD
1.3V
Output
3300
50 pF


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