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CS7622-IQ 数据表(PDF) 9 Page - Cirrus Logic

部件名 CS7622-IQ
功能描述  CCD Imager Analog Processor
Download  36 Pages
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制造商  CIRRUS [Cirrus Logic]
网页  http://www.cirrus.com
标志 CIRRUS - Cirrus Logic

CS7622-IQ 数据表(HTML) 9 Page - Cirrus Logic

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CS7622
DS322PP1
9
a fixed gain of 1x is selected, DOUT[12:3] is used
as the output, a fixed gain of 2x will use
DOUT[11:2], etc. In order to use this mode, the
fixed gain register (14h) should be set and the cali-
bration offset registers (OEh - 10h) should be set to
0.
The CDS/VGA circuit is composed of three stages.
The first stage has a fixed gain of 1, and the second
and third stages have variable gain with a combined
gain range of 1 to 8 (0-18 dB). Figure 8 shows a
block diagram of the CDS/VGA circuit. The total
gain is A = (C2/C3)(C4/C5) which is adjusted by
varying C3 and C5. The capacitor Cb on the front
of stage 1 is for black level adjustment and will be
discussed in detail later.
This circuit utilizes a two phase non-overlapping
clock to perform the desired CDS function. The
two phase clock also allows the video signal to be
passed to the output while retaining a positive po-
larity signal. Figure 9 shows a timing diagram of
the two phase clock along with the CCD signal and
output signals of stages one, two and three.
There is an internal mid-scale DC bias level circuit
at the input pin. This allows AC coupling into the
CS7622 with a capacitor and having the input auto-
VOUT (V)
VIN (V)
1.0
0.5
0.25
0.125
1.07
0.5
1X
2X
4X
8X
ADC OUTPUT
00
01
10
11
Figure 7. Transfer function of VGA circuit (assuming full scale level of 1.0 V)
-A2
-A3
C2
C3
C4
C5
Φ1
Φ2
STAGE 2
STAGE 3
VOUT
Vo1
-A1
C1
C1
Φ1
VIN
ADC
Vo2
STAGE 1
CONTROLS C3, C5
CONTROLS GAIN ADJUST BLOCK IN DIGITAL
2
Cb
VREF
Figure 8. Block diagram of CDS/VGA circuit
100 K
100 K


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