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AD5601BKS 数据表(PDF) 5 Page - Analog Devices

部件名 AD5601BKS
功能描述  2.7 V to 5.5 V, <100 UA, 8-/10-/12-Bit nanoDAC D/A, SPI Interface, SC70 Package
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5601BKS 数据表(HTML) 5 Page - Analog Devices

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Preliminary Technical Data
AD5601/AD5611/AD5621
Rev. PrC | Page 5 of 20
B Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
2.7
5.5
V
All digital inputs at 0 or VDD
IDD (Normal Mode)
DAC active and excluding load current
VDD = ±4.5 V to ±5.5 V
100
µA
VIH = VDD and VIL = GND
VDD = ±2.7 V to ±3.6 V
70
µA
VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = ±4.5 V to ±5.5 V
0.2
1
µA
VIH = VDD and VIL = GND
VDD = ±2.7 V to ±3.6 V
0.05
1
µA
VIH = VDD and VIL = GND
POWER EFFICIENCY
IOUT/IDD
TBD
%
ILOAD = 2 mA and VDD = ±5 V
1 Temperature ranges are as follows: B Version: –40°C to +125°C, typical at +25°C.
2 Linearity calculated using a reduced code range.
3 Guaranteed by design and characterization, not production tested.
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 3.
Parameter
Limit1
Unit
Test Conditions/Comments
t12
33
ns min
SCLK cycle time
t2
13
ns min
SCLK high time
t3
12
ns min
SCLK low time
t4
13
ns min
SYNC to SCLK falling edge setup time
t5
5
ns min
Data setup time
t6
4.5
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
33
ns min
Minimum SYNC high time
t9
13
ns min
SYNC rising edge to next SCLK fall ignore
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
t4
t3
t2
t5
t7
t6
D0
D1
D2
D14
D15
DIN
SYNC
SCLK
t9
t1
t8
D15
D14
Figure 2. Timing Diagram


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