TLF11675

October 1995

74VHC4046

CMOS Phase Lock Loop

General Description

The 74VHC4046 is a low power phase lock loop utilizing

advanced silicon-gate CMOS technology to obtain high fre-

quency operation both in the phase comparator and VCO

sections This device contains a low power linear voltage

controlled oscillator (VCO) a source follower and three

phase comparators The three phase comparators have a

common signal input and a common comparator input The

signal input has a self biasing amplifier allowing signals to

be either capacitively coupled to the phase comparators

with a small signal or directly coupled with standard input

logic levels This device is similar to the CD4046 except that

the Zener diode of the metal gate CMOS device has been

replaced with a third phase comparator

Phase Comparator I is an exclusive OR (XOR) gate It pro-

vides a digital error signal that maintains a 90 phase shift

between the VCO’s center frequency and the input signal

(50% duty cycle input waveforms) This phase detector is

more susceptible to locking onto harmonics of the input fre-

quency than phase comparator I but provides better noise

rejection

Phase comparator III is an SR flip-flop gate It can be used

to provide the phase comparator functions and is similar to

the first comparator in performance

Phase comparator II is an edge sensitive digital sequential

network Two signal outputs are provided a comparator out-

put and a phase pulse output The comparator output is a

TRI-STATE

output that provides a signal that locks the

VCO output signal to the input signal with 0 phase shift be-

tween them This comparator is more susceptible to noise

throwing the loop out of lock but is less likely to lock onto

harmonics than the other two comparators

In a typical application any one of the three comparators

feed an external filter network which in turn feeds the VCO

input This input is a very high impedance CMOS input

which also drives the source follower The VCO’s operating

frequency is set by three external components connected to

the C1A C1B R1 and R2 pins An inhibit pin is provided to

disable the VCO and the source follower providing a meth-

od of putting the IC in a low power state

The source follower is a MOS transistor whose gate is con-

nected to the VCO input and whose drain connects the De-

modulator output This output normally is used by tying a

resistor from pin 10 to ground and provides a means of

looking at the VCO input without loading down modifying the

characteristics of the PLL filter

Features

Y

Low dynamic power consumption

Y

Maximum VCO operating frequency

12 MHz

Y

Comparator I

25 ns

Comparator II

30 ns

Comparator III

25 ns

Y

VCO has high linearity and high temperature stability

Y

Pin and function compatible with the 74HC4046

Commercial

Package

Package Description

Number

74VHC4046M

M16A

16-Lead Molded JEDEC SOIC

74VHC4046N

N16E

16-Lead Molded DIP

Note

Surface mount packages are also available on Tape and Reel Specify by appending the suffix letter ‘‘X’’ to the ordering code

TRI-STATE

is a registered trademark of National Semiconductor Corporation

C1995 National Semiconductor Corporation

RRD-B30M125Printed in U S A