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MC10H125M 数据表(PDF) 2 Page - ON Semiconductor |
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MC10H125M 数据表(HTML) 2 Page - ON Semiconductor |
2 / 8 page MC10H125 http://onsemi.com 2 LOGIC DIAGRAM PIN ASSIGNMENT VBB Ain Ain Aout Bout Bin Bin VEE GND Din Din Dout Cout Cin Cin VCC 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 4 3 2 5 7 6 12 11 10 13 15 14 1 GND = Pin 16 VCC ( +5.0 Vdc) = Pin 9 VEE ( -5.2 Vdc) = Pin 8 *VBB to be used to supply bias to the MC10H125 only and bypassed (when used) with 0.01 mF to 0.1 mF capacitor to ground (0 V). VBB can source < 1.0 mA. VBB* Pin assignment is for Dual-in-Line Package. For PLCC pin assignment, see the Pin Conversion Tables. DIP CONVERSION TABLES 16-Pin DIL to 20-Pin PLCC 16 PIN DIL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 PIN PLCC 2 3 4 5 7 8 9 10 12 13 14 15 17 18 19 20 20-Pin DIL to 20-Pin PLCC 20 PIN DIL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 20 PIN PLCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 |
类似零件编号 - MC10H125M |
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类似说明 - MC10H125M |
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