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LM2501 数据表(PDF) 5 Page - National Semiconductor (TI) |
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LM2501 数据表(HTML) 5 Page - National Semiconductor (TI) |
5 / 14 page Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2) Symbol Parameter Conditions Min Typ Max Units PARALLEL BUS TIMING t SET Set Time - Data to Clock Inputs Figure 2 TBD ns t HOLD Hold Time - Clock to Data TBD ns t RISE Rise Time Outputs, C L =15pF ns t FALL Fall Time ns PC LOW PCLK Low 50 % PC HIGH PCLK High 50 % t DVBC Data Valid before Clock Figure 2 TBD ns t DVAC Data Valid after Clock TBD ns SERIAL BUS TIMING t DVBC Figure 1 t DVAC POWER UP TIMING (see Figures 5, 6) t 1 WC Start Up Delay Figure 5 Planned Rev G ES test Chip will double WC cyc counts on T 1 to T4 (SER) parameters to support higher WC rates. 100 WC CYC t 2 WC Low Initialization Low State 11 12 13 WC CYC t 3 WC Pulse Width High 11 12 13 WC CYC t 4 WC Low State 11 12 13 WC CYC t 5 WC IN to WCOUT Latency (SER) 678 WC CYC t 6 TBD 9WC CYC t 7 SER PLL Lock Time Figure 6 4,096 MC CYC t 8 MC Low Initialization Low State 11 12 13 MC CYC t 9 MC Pulse Width High 11 12 13 MC CYC t 10 MC Low State 11 12 13 MC CYC t 11 SER Latency TBD MC CYC t 12 DES Latency TBD MC CYC POWER OFF TIMING t PAZ Disable Time to Power Off µs t PZA Enable Time from Power Off µs www.national.com 5 |
类似零件编号 - LM2501 |
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类似说明 - LM2501 |
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