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CY7C1618KV18 数据表(PDF) 9 Page - Cypress Semiconductor

部件名 CY7C1618KV18
功能描述  144-Mbit DDR II SRAM Two-Word Burst Architecture
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制造商  CYPRESS [Cypress Semiconductor]
网页  http://www.cypress.com
标志 CYPRESS - Cypress Semiconductor

CY7C1618KV18 数据表(HTML) 9 Page - Cypress Semiconductor

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Document Number: 001-44274 Rev. *N
Page 9 of 32
CY7C1618KV18/CY7C1620KV18
Truth Table
The truth table for the CY7C1618KV18, and CY7C1620KV18 follow: [2, 3, 4, 5, 6, 7]
Operation
K
LD
R/W
DQ
DQ
Write cycle:
Load address; wait one cycle;
input write data on consecutive K and K rising edges.
L–H
L
L
D(A1) at K(t + 1)
 D(A2) at K(t + 1) 
Read cycle:
Load address; wait one and a half cycle;
read data on consecutive C and C rising edges.
L–H
L
H
Q(A1) at C(t + 1)
 Q(A2) at C(t + 2) 
NOP: No operation
L–H
H
X
High Z
High Z
Standby: Clock stopped
Stopped
X
X
Previous state
Previous state
Burst Address Table
(CY7C1618KV18, CY7C1620KV18)
First Address (External)
Second Address (Internal)
X..X0
X..X1
X..X1
X..X0
Notes
2. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,
represents rising edge.
3. Device powers up deselected with the outputs in a tristate condition.
4. On CY7C1618KV18 and CY7C1620KV18, “A1” represents address location latched by the devices when transaction was initiated and “A2” represents the addresses
sequence in the burst.
5. “t” represents the cycle at which a read/write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. Ensure that when clock is stopped K = K and C = C = high. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.


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类似说明 - CY7C1618KV18

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