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CY7C1460KV25 数据表(PDF) 31 Page - Cypress Semiconductor |
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CY7C1460KV25 数据表(HTML) 31 Page - Cypress Semiconductor |
31 / 32 page Document Number: 001-66679 Rev. *J Page 31 of 32 CY7C1460KV25/CY7C1462KV25 CY7C1460KVE25/CY7C1462KVE25 Document History Page Document Title: CY7C1460KV25/CY7C1462KV25/CY7C1460KVE25/CY7C1462KVE25, 36-Mbit (1M × 36/2M × 18) Pipelined SRAM with NoBL™ Architecture (With ECC) Document Number: 001-66679 Revision ECN Orig. of Change Submission Date Description of Change *E 4680535 PRIT 04/10/2015 Changed status from Preliminary to Final. *F 4757974 DEVM 05/07/2015 Updated Functional Overview: Updated ZZ Mode Electrical Characteristics: Changed maximum value of IDDZZ parameter from 89 mA to 75 mA. *G 5028596 PRIT 11/26/2015 Added Errata. *H 5210861 DEVM 04/07/2016 Removed Errata. Updated to new template. Completing Sunset Review. *I 5337537 PRIT 07/05/2016 Updated Neutron Soft Error Immunity: Updated values in “Typ” and “Max” columns corresponding to LSBU (Device without ECC) parameter. *J 6062214 CNX 02/07/2018 Updated Package Diagrams: spec 51-85050 – Changed revision from *E to *G. Updated to new template. |
类似零件编号 - CY7C1460KV25 |
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类似说明 - CY7C1460KV25 |
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