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SLG46534 数据表(PDF) 11 Page - Dialog Semiconductor |
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SLG46534 数据表(HTML) 11 Page - Dialog Semiconductor |
11 / 172 page SLG46534_DS_107 Page 10 of 171 SLG46534 5.5 I2C Specifications 5.6 Asynchronous State Machine (ASM) Specifications VO Maximal Voltage Applied to any PIN in High-Impedance State -- -- VDD V TSU Startup Time From VDD rising past PONTHR 0.60 1.23 1.61 ms PONTHR Power On Threshold VDD Level Required to Start Up the Chip 1.41 1.54 1.66 V POFFTHR Power Off Threshold VDD Level Required to Switch Off the Chip 1.00 1.15 1.31 V RPUP Pull Up Resistance 1 M Pull Up 864.6 1093.4 1348.1 k 100 k Pull Up 84.32 108.97 135.24 k 10 k Pull Up 8.74 11.37 14.52 k RPDWN Pull Down Resistance 1 M Pull Down 873.3 1096.1 1370.5 k 100 k Pull Down 87.57 109.48 135.89 k 10 k Pull Down 7.95 11.33 14.78 k Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11, 12, 13 and 14 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit FSCL Clock Frequency, SCL VDD = (1.71...5.5) V -- -- 400 kHz tLOW Clock Pulse Width Low VDD = (1.71...5.5) V 1300 ns tHIGH Clock Pulse Width High VDD = (1.71...5.5) V 600 -- -- ns tI Input Filter Spike Suppression (SCL, SDA) VDD = 1.8 V ± 5 % -- -- 95 ns VDD = 3.3 V ± 10% 95 VDD = 5.0 V ± 10 % 111 tAA Clock Low to Data Out Valid VDD = (1.71...5.5) V -- -- 900 ns tBUF Bus Free Time between Stop and Start VDD = (1.71...5.5) V 1300 -- -- ns tHD_STA Start Hold Time VDD = (1.71...5.5) V 600 -- -- ns tSU_STA Start Set-up Time VDD = (1.71...5.5) V 600 -- -- ns tHD_DAT Data Hold Time VDD = (1.71...5.5) V 0 -- -- ns tSU_DAT Data Set-up Time VDD = (1.71...5.5) V 100 -- -- ns tR Inputs Rise Time VDD = (1.71...5.5) V -- -- 300 ns tF Inputs Fall Time VDD = (1.71...5.5) V -- -- 300 ns tSU_STO Stop Set-up Time VDD = (1.71...5.5) V 600 -- -- ns tDH Data Out Hold Time VDD = (1.71...5.5) V 50 -- -- ns Symbol Parameter Condition/Note Min. Typ. Max. Unit tst_out_delay Asynchronous State Machine Output Delay Time VDD = 1.8 V ± 5 % 225 -- 275 ns VDD = 3.3 V ± 10% 95 118 VDD = 5.0 V ± 10 % 67 -- 77 Symbol Parameter Condition/Note Min. Typ. Max. Unit |
类似零件编号 - SLG46534 |
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类似说明 - SLG46534 |
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