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SLG46534 数据表(PDF) 90 Page - Dialog Semiconductor |
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SLG46534 数据表(HTML) 90 Page - Dialog Semiconductor |
90 / 172 page SLG46534_DS_107 Page 89 of 171 SLG46534 10.0 Analog Comparators (ACMP) There are three Analog Comparator (ACMP) macrocells in the SLG46534. In order for the ACMP cells to be used in a GreenPAK design, the power up signals (ACMPx_pdb) need to be active. By connecting to signals coming from the Connection Matrix, it is possible to have each ACMP be always on, always off, or power cycled based on a digital signal coming from the Connection Matrix. Also, all ACMPs have Wake and Sleep function (WS), see section 9.10 Wake and Sleep controller (WS). When ACMP is powered down, output is low. PWR UP = 1 => ACMP is powered up. PWR UP = 0 => ACMP is powered down. During ACMP power up, its output will remain low, and then becomes valid 1.03 ms (max) after ACMP power up signal goes high, see Figure 51. If VDD is greater or equal to 2.7 V, it is possible to decrease turn-on time by setting the BG ok delay to 100 μs, see Figure 52. The ACMP cells have an input "Low bandwidth" signal selection, which can be used to save power and reduce noise impact when lower bandwidth signals are being compared. To ensure proper chip startup operation, it is recommended to enable the ACMPs with the POR signal, and not the VDD signal. Note: Regulator and Charge Pump set to automatic ON/OFF . Figure 50. Maximum Power On Delay vs. VDD, BG = Auto-delay. 120 140 160 180 200 220 240 VDD (V) -40⁰C +25⁰C +85⁰C |
类似零件编号 - SLG46534 |
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类似说明 - SLG46534 |
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