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SLG46169 数据表(PDF) 90 Page - Dialog Semiconductor |
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SLG46169 数据表(HTML) 90 Page - Dialog Semiconductor |
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90 / 102 page  000-0046169-105 Page 89 of 101 SLG46169 reg<784:782> Counter/delay6 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter5 Overflow reg<792:785> Counter6 Control Data/Delay6 Time Control 1-256: (delay time = (counter control data +2) /freq) reg<794:793> Delay6 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<799:795> ACMP0 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: Reserved 11011: EXT_VREF(PIN6) reg<801:800> ACMP0 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg<803:802> ACMP0 positive Input divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X reg<804> ACMP0 low bandwidth (Max: 1 MHz) enable 0: off 1: on reg<805> ACMP0 positive input source select VDD 0: Disabled 1: Enabled reg<810:806> ACMP1 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: Reserved 11011: Reserved Register Bit Address Signal Function Register Bit Definition |
类似零件编号 - SLG46169 |
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类似说明 - SLG46169 |
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