CS53L32A

10

DS513F1

8.

There must be exactly 32, 48, 64, or 128 SCLK periods per LRCK transition.

9. Slave Mode operation requires an exact 50% duty cycle. Otherwise the CS53L32A will produce

erroneous data.

Parameters

Symbol

Min

Typ

Max

Units

Input Sample Rate

Base Rate Mode

High Rate Mode

Fs

Fs

2

50

-

-

50

100

kHz

kHz

MCLK Pulse Width High

MCLK/LRCK = 1024

8

-

-

ns

MCLK Pulse Width Low

MCLK/LRCK = 1024

8

-

-

ns

MCLK Pulse Width High

MCLK/LRCK = 768

10

-

-

ns

MCLK Pulse Width Low

MCLK/LRCK = 768

10

-

-

ns

MCLK Pulse Width High

MCLK/LRCK = 512

15

-

-

ns

MCLK Pulse Width Low

MCLK/LRCK = 512

15

-

-

ns

MCLK Pulse Width High

MCLK / LRCK = 384 or 192

21

-

-

ns

MCLK Pulse Width Low

MCLK / LRCK = 384 or 192

21

-

-

ns

MCLK Pulse Width High

MCLK / LRCK = 256 or 128

31

-

-

ns

MCLK Pulse Width Low

MCLK / LRCK = 256 or 128

31

-

-

ns

Master Mode

SCLK Falling to LRCK Edge

-20

-

20

ns

SCLK Falling to SDOUT Valid

0

-

20

ns

SCLK Duty Cycle

40

50

60

%

Slave Mode

LRCK Duty Cycle

Notes 8, 9

-

50

-

%

Rise Time of Both LRCK and SCLK

-

-

10

ns

Fall Time of Both LRCK and SCLK

-

-

10

ns

SCLK Period

Base Rate Mode

High Rate Mode

-

-

-

-

ns

ns

SCLK Falling to LRCK Edge

-20

-

20

ns

SCLK Falling to SDOUT Valid

Base Rate Mode

High Rate Mode

-

-

-

-

ns

ns

NOTE: When operating the CS53L32A Revision C in Slave Mode, Base Rate Mode, certain timing requirements

must be met in addition to those specified above. The required timing relationship between the MCLK and LRCK

is shown in Figures 3. An MCLK rising edge cannot lead an LRCK transition by 6ns to 10ns.

1

128

()Fs

----------------------

1

64

()Fs

------------------

1

(512)Fs

1

(256)Fs