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HCF4029BEY 数据表(PDF) 8 Page - STMicroelectronics |
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HCF4029BEY 数据表(HTML) 8 Page - STMicroelectronics |
8 / 12 page HCF4029B 8/12 (*) Typical temperature coefficient for all VDD value is 0.3 %/°C. (1) If more than one unit is cascated in the parallel clocked application tr should be made less than or equal to the sum of the fixed propagation delay at 15pF and the transition time of the carry output driving stage for the estimated capacitance load. (2) From Up/Down, Binary/Decade, Carry In or Preset Enable Control Inputs to Clock Edge. (3) From Carry In to Clock Edge. TEST CIRCUIT CL = 50pF or equivalent (includes jig and probe capacitance) RL = 200KΩ RT = ZOUT of pulse generator (typically 50Ω) PRESET ENABLE tPHL tPLH Propagation Delay Time (Carry Output) 5 170 340 ns 10 70 140 15 50 100 tsetup (3) Minimum Setup Time (Carry In) 525 50 ns 10 15 30 15 12 25 thold Minimum Hold Time (Carry In) 5 100 200 ns 10 35 70 15 30 60 Symbol Parameter Test Condition Value (*) Unit VDD (V) Min. Typ. Max. |
类似零件编号 - HCF4029BEY |
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类似说明 - HCF4029BEY |
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