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TSB41BA3PFP 数据表(PDF) 4 Page - Texas Instruments |
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TSB41BA3PFP 数据表(HTML) 4 Page - Texas Instruments |
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4 / 63 page  TSB41BA3 IEEE 1394b THREEPORT CABLE TRANSCEIVER/ARBITER SLLS155A − MAY 2003 − REVISED OCTOBER 2003 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 description (continued) To operate a port as a 1394b bilingual port, the speed/mode selections terminals (S5_LKON_DS2, S4_DS1, S3_DS0, S2_PC0, S1_PC1, and S0_PC2) need to be pulled to VCC or ground through a 1-k Ω resistor. The port must be operated in the 1394b bilingual mode whenever a 1394b bilingual or a 1394b beta-only connector is connected to the port. To operate the port as a 1394a-only port, the speed/mode selection terminals must be configured correctly to force 1394a-2000-only operation on that port. The only time the port must be forced to the data-strobe-only mode is if the port is connected to a 1394a connector (either 6-pin, which is recommended, or 4-pin). This mode is provided to ensure that 1394b signaling is never sent across a 1394a cable. NOTE:A bilingual port can only connect to a 1394b-only port that operates at S400b. It can not establish a connection to a S200b or S100b port. A port that has been forced to S400b (B4) can connect to a 1394b-only port at S400b (B4) or S200b (B2) or S100b (B1). A port that has been forced to S200b can connect to a 1394b-only port at S200b or S100b. A port that has been forced to S100b can only connect to a 1394b-only port at S100b. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal must be connected to VDD through a 1-kΩ resistor. The SE and SM terminals must be tied to ground through a 1-k Ω resistor. Three package terminals are used as inputs to set the default value for three configuration status bits in the self-ID packet. They may be pulled high through a 1-k Ω resistor or hardwired low as a function of the equipment design. In some speed/mode selections the S2_PC0, S1_PC1, and S0_PC2 terminals indicate the default power class status for the node (the need for power from the cable or the ability to supply power to the cable), please see Table 1. The contender bit in the PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM) or for the bus manager (BM). On the TSB41BA3, this bit may only be set by a write to the PHY register set. If a node desires to be a contender for IRM or BM, then the node software must set this bit in the PHY register set. The LPS (link power status) terminal works with the S5_LKON_DS2 terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 2 and Table 3 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC. The LPS signal also resets, disables, and initializes the PHY-LLC interface (the state of the PHY-LCC interface is controlled solely by the LPS input regardless of the state of the LCtrl bit). NOTE:The TSB41BA3 does not have a cable-not-active (CNA) pin. To achieve a similar function, the individual PHY ports may be set-up to issue interrupts whenever the port changes state. If the LPS pin is low, then this generates a link-on (LKON) output clock. Please see register bits PIE, PEI, and WDIE along with the individual interrupt bits. The LPS input is considered inactive if it remains low for more than the LPS_RESET time (see the LPS terminal definition) and is considered active otherwise. When the TSB41BA3 detects that the LPS input is inactive, the PHY-LLC interface is placed into a low-power reset state in which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see the LPS terminal definition), then the PHY-LLC interface is put into a low-power disabled state in which the PCLK output is also held inactive. The TSB41BA3 continues the necessary repeater functions required for normal network operation regardless of the state of the PHY-LLC interface. When the interface is in the reset or disabled state and the LPS input is again observed active, the PHY initializes the interface and returns to normal operation. The PHY-LLC interface is also held in the disabled state during hardware reset. When the LPS terminal is returned to an active state after being sensed as having entered the LPS_DISABLE time, the TSB41BA3 issues a bus reset. This broadcasts the node self-ID packet, which contains the updated L bit state (the PHY LLC now being accessible). The PHY uses the S5_LKON_DS2 terminal to notify the LLC to power up and become active. When activated, the output S5_LKON_DS2 signal is a square wave. The PHY activates the S5_LKON_DS2 output when the LLC is inactive and a wake-up event occurs. The LLC is considered inactive when either the LPS input is inactive, as described above, or the LCtrl bit is cleared to 0. A wake-up event occurs when a link-on PHY packet |
类似零件编号 - TSB41BA3PFP |
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类似说明 - TSB41BA3PFP |
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